🛠️Vacancy: Design Verification Engineer - Apple
🎯Tasks
- Development and implementation of RTL/SoC verification plans.
- Creation of a test environment (SystemVerilog, UVM).
- Coverage analysis, error debugging, interaction with designers.
✅ Requirements
- Higher education in electrical or computer engineering.
- Experience in digital verification (ASIC/SoC).
- Knowledge of SystemVerilog, UVM, Python/Perl/TCL.
💡 It will be a plus
- Experience with low-power systems, PHY, PCIe, DDR.
- Knowledge of formal methods and SoC architecture.
🚀 Why Apple
- Work on key components of future devices.
- Global projects, strong team, modern environment.
📩 Apply and become part of the team that creates the technologies of the future